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Push-Pull FET Driver with Integrated Oscillator
and Programmable Clock Output
Detailed Description
Table 1. CLK Output Frequency Selection
The MAX5077 is a +4.5V to +15V push-pull, current-fed
topology driver subsystem with an integrated oscillator
for use in 48V module power supplies.
SEL2
SEL1
f CLK
f NRDV_
f CLK to f NDRV
RATIO
The MAX5077 features a programmable accurate inte-
Low
Low
NDRV1, NDRV2, and CLK disabled
grated oscillator with a synchronizing clock output that
can be used to synchronize an external PWM stage. A
single external resistor programs the internal oscillator
frequency from 50kHz to 1.5MHz.
Low
High
High
High
Low
High
f OSC / 2
f OSC
f OSC
f OSC / 2
f OSC / 2
f OSC / 4
1
2
4
The MAX5077 incorporates dual MOSFET drivers with
±3A peak drive currents and a 50% duty cycle. The
MOSFET drivers generate complementary signals to
drive external ground-referenced n-channel MOSFETs.
The MAX5077 CLK output frequency is programmable
through logic inputs that set the f CLK :NDRV_ ratio to 1x,
2x, or 4x.
Internal Oscillator
An external resistor at RT programs the MAX5077’s
internal oscillator frequency from 50kHz to 1.5MHz. The
MAX5077 NDRV1 and NDRV2 switching frequencies
are one-half or one-fourth the programmed oscillator
frequency with a nominal 50% duty cycle.
Use the following formula to calculate the internal oscil-
NDRV1
NDRV2
CLK
OSC
NDRV1
NDRV2
CLK
SEL2 = 0, SEL1 = 0
lator frequency:
OSC
f OSC =
10 12
32 × R RT
SEL2 = 0, SEL1 = 1
where f OSC is the oscillator frequency and R RT is a
resistor connected from RT to AGND in ohms.
Place a series combination of a 4.7k ? resistor and a
1nF capacitor from RT to AGND for stability and to filter
out noise.
When the f CLK :f NDRV_ ratio is set to 4, the NDRV1 and
NDRV2 switching frequency is limited to one-fourth
f OSC . When operating the MAX5077 with the
f CLK :f NDRV_ ratios set to 1 or 2 (see the Synchronizing
Clock Output section), the NDRV1 and NDRV2 switch-
ing frequency is set to one-half f OSC .
Synchronizing Clock Output
The MAX5077 provides a buffered clock output that can
be used to synchronize the oscillator input of a PWM
controller. CLK is powered from an internal 5V regulator
and sources/sinks up to 10mA. Two logic inputs (SEL2,
SEL1) select CLK output frequency to 1x, 2x, or 4x with
NDRV1
NDRV2
CLK
OSC
NDRV1
NDRV2
CLK
SEL2 = 1, SEL1 = 0
respect to NDRV1 and NDRV2 switching frequency (see
Table 1 and Figure 2). Drive SEL2 and SEL1 low to
disable NDRV1, NDRV2, and CLK outputs. There is a
OSC
SEL2 = 1, SEL1 = 1
typical 30ns delay from CLK to NDRV_ output.
Figure 2. MAX5077 CLK Timing Diagram
6
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